The invention pertains to silicon-on-insulator (SOI) transistor technology and particularly to SOI transistor substrates. More particularly, the invention pertains to silicon-on-insulator fabrication.
SOI technology has been an active area of development since the late nineteen seventies due to its potential for superior performance compared to bulk silicon devices for high speed and very large scale integration (VLSI) integrated circuit applications. In addition, SOI devices, circuits, and systems can provide satisfactory performance under harsh environments such as high energy radiation, and high temperatures (e.g., greater than 300 degrees Centigrade), associated with military, space, and automobile applications. At present, while some SOI circuits (mainly based on thick film having a thickness greater than 0.3 microns) are in production, the full potential of the SOI technology has not been realized primarily due to the difficulties in the fabrication of the SOI structure with the necessary silicon thickness value, thickness uniformity, and low defect (dislocation) densities. For example, high speed and low noise circuits, and high temperature and radiation-hard applications require a fully depleted mode of SOI device operation. This operation in turn requires defect-free silicon films having a very small thickness (less than 0.25 micron) and uniform thickness (less than a plus or minus 50 Angstroms variation). These thin film characteristics have not been satisfactorily achieved using related-art SOI fabrication technologies.
FIG. 1 is a diagram of a related-art schematic of the separation by implantation of oxygen (SIMOX) process for fabricating SOI substrates. The SIMOX process is the predominantly used process. The process involves a high dose (about 1.8.times.10.sup.18 /cm.sup.2) implantation of oxygen atoms 12 at an energy of about 200 KeV into silicon wafer 14. After the implantation, wafer 14 is annealed at about 1300 degrees Centigrade (C.) for a long duration, that is, about five hours, resulting in a buried SiO.sub.2 layer 16, and a thin silicon layer 17. SIMOX process results in excellent silicon thickness control and uniformity, which was the reason for its early acceptance. However, the disadvantages of the SIMOX process include high defect density in silicon, and layer 17 pinhole defects in the oxide layer. Oxide pinhole defects are a consequence of the particulate shadowing of the oxygen ion beam during implantation. Pinhole defects result in low device yields. In spite of the extensive annealing after implantation, the dislocation density in the SIMOX material is high and ranges from 10.sup.5 to 10.sup.6 /cm.sup.2. This high defect density limits the maximum achievable performance of the resulting CMOS circuits and limits high speed and low noise in bipolar circuits. Due to these limitations of the SIMOX process, several variations of a bonding and etch-back SOI (BESOI) approach have been tried.
FIG. 2 shows one variation of the BESOI approach which does not involve use of an etch-stop layer. In this process, a silicon handle wafer 18 and the silicon device wafer 20 having an oxide layer 22 are fusion bonded at about 1000 degrees C. This results in an intimate bonding of the two silicon wafers 18 and 20, with buried oxide layer 22 in between. Then most of the device wafer 20 is removed by grinding and lapping. This is followed by a final high precision chemical/mechanical polishing. While the silicon device layer produced using this approach is defect free, its thickness is typically about 2 microns, (with a plus or minus 0.5 micron variation). The large thickness value and the large thickness variation are not satisfactory for the SOI devices requiring a fully depleted mode of operation.
FIG. 3 shows the second variation of the BESOI approach which involves use of an etch-stop layer 23. In this process, a silicon handle wafer 18 with a buried oxide layer 22, and a silicon device wafer 20 (p.sup.-) with the etch-stop layer 23 and epitaxial layer 21 are fusion bonded together at about 1000 degrees C. Buried oxide 22 on silicon handle wafer 18 is prepared by thermal oxidation. Etch-stop layer 23 is essentially a highly boron doped (p.sup.++) single crystal silicon layer. It is produced by epitaxial deposition. After depositing the etch-stop layer, a lightly boron doped (p.sup.-) silicon device layer 21, with the desired thickness is epitaxially deposited. After the fusion bonding, the SOI substrate preparation process involves grinding (to remove most of silicon device wafer 20), and preferential chemical etching to remove the remaining silicon device wafer 20, and etch-stop layer 23. Unfortunately, due to inter-diffusion of the boron from the highly doped etch-stop layer 23 into thin lightly doped device layer 21 during the high temperature fusion bonding process, reliability of the etch-stop layer is severely affected. Furthermore, control of the device layer 21 thickness and its uniformity become very difficult, thereby resulting in an unsatisfactory process for obtaining a thin, uniform silicon device layer for a fully depleted mode of SOI device operation. This approach has not been very successful.
FIG. 4 shows the localized plasma thinning approach. This process starts with an SOI wafer such as the one produced by BESOI process without an etch-stop 23 (of FIG. 2), with a thick silicon film 21 of typically about 2 microns with a thickness variation of about plus or minus 0.5 micron. Initially, silicon film thickness and its uniformity across the SOI wafer surface are measured and mapped. Using this thickness profile information, a localized plasma etching apparatus 24 is utilized to locally etch the device layer 21 with CF.sub.4 +O.sub.2 plasma, while the SOI substrate is being translated in a pre-programmed fashion under apparatus 24, to reduce the thickness of the silicon film 21 to the desired value. The thickness mapping and localized etching procedures may be repeated as required to achieve the desired silicon device layer 21 thickness and uniformity at a value between 0.1 to 0.3 microns and the thickness having a surface variation of about plus or minus 100 Angstroms. While the basic feasibility of this localized thinning approach has been demonstrated, the cost of this process is high and the plasma etched silicon surface imposes limitations to the performance of the devices fabricated. Plasma etching damages the surface quality of the silicon film by increasing the surface state density. Increased surface state density affects the performance of the surface sensitive devices such as CMOS transistors. In contrast, chemical etching results in a higher quality surface with a low surface state density which allows fabrication of superior CMOS devices.
Thus, there is still a need for the development of a process to produce SOI substrates with defect free, thin, uniform silicon films with high quality chemically etched surfaces, and high quality thermally formed buried oxide dielectric, for fully depleted mode of device operation, at low cost. The present invention is the answer to that need.